11 #include "boost/bind.hpp"
56 Bool_t local_debug =
false;
58 if(local_debug) printf(
"\n------------- R1 LoadChannelMap %s\n\n", mapfile.Data());
61 TString varvalue =
"";
65 Int_t slot_number = 0;
66 Int_t chan_number = 0;
67 Int_t fiber_number = 0;
69 Int_t reference_counter = 0;
78 while (mapstr.ReadNextLine()){
80 mapstr.TrimComment(
'!');
81 mapstr.TrimWhitespace();
83 if (mapstr.LineIsEmpty())
continue;
85 if (mapstr.HasVariablePair(
"=",varname,varvalue)){
90 value = atol(varvalue.Data());
95 else if (varname==
"bank"){
98 else if (varname==
"pkg") {
101 else if (varname==
"slot") {
107 modtype = mapstr.GetTypedNextToken<TString>();
108 slot_number = mapstr.GetTypedNextToken<Int_t>();
109 chan_number = mapstr.GetTypedNextToken<Int_t>();
110 fiber_number = mapstr.GetTypedNextToken<Int_t>();
111 name = mapstr.GetTypedNextToken<TString>();
114 printf(
"Modtype %8s Slot_Number %4d ChanN %4d, FiberN %4d, FiberName %s\n", modtype.Data(), slot_number, chan_number, fiber_number, name.Data());
116 if (modtype==
"F1TDC") {
118 if (fiber_number==99) {
122 if (name==
"MasterTrigger" ) {
142 else if (modtype ==
"SIS3801") {
150 localchannel.SetNeedsExternalClock(kFALSE);
151 fSCAs.push_back(localchannel);
153 fSCAs_offset.push_back( QwSIS3801D24_Channel::GetBufferOffset(slot_number,chan_number) );
172 Int_t unused_size_counter = 0;
179 for(
size_t slot_size =0; slot_size <
fModuleIndex.at(i).size(); slot_size++)
184 std::cout <<
"[" << i <<
","<< slot_size <<
"] "
189 unused_size_counter++;
196 printf(
"Total unused size of fModuleIndex vector %6d\n", unused_size_counter);
200 std::cout <<
"[" << i <<
"] "
219 printf(
"\n------------- R1 LoadChannelMap End%s\n\n", mapfile.Data());
248 for (i=0; i<
fSCAs.size(); i++) {
249 fSCAs.at(i).ClearEventData();
266 for (i=0; i<
fSCAs.size(); i++)
268 fSCAs.at(i).ProcessEvent();
285 for (std::size_t i=0; i<
fSCAs.size(); i++) {
286 fSCAs.at(i).ConstructHistograms(folder, prefix);
295 for (std::size_t i=0; i<
fSCAs.size(); i++) {
296 fSCAs.at(i).FillHistograms();
314 std::vector<Double_t> &values)
319 if (prefix==
"") basename =
"scifiber";
320 else basename = prefix;
324 for (std::size_t i=0; i<
fSCAs.size(); i++)
326 if (
fSCAs.at(i).GetElementName() !=
"") {
327 values.push_back(0.0);
328 list +=
":" +
fSCAs.at(i).GetElementName() +
"/D";
333 list = list(1,list.Length()-1);
348 for (std::size_t i=0; i<
fSCAs.size(); i++)
350 if (
fSCAs.at(i).GetElementName() !=
"") {
351 values[index] =
fSCAs.at(i).GetValue();
376 Int_t bank_index = 0;
377 Int_t module_index = 0;
380 UInt_t vme_slot_num = 0;
382 std::cout <<
"QwSciFiDetector Region : "
384 <<
"::ReportConfiguration fDetectorIDs.size() "
393 for ( j=0; j<
fBank_IDs.at(i).size(); j++ )
396 if(bank_flag == 0)
continue;
404 std::cout <<
"ROC [index, Num]["
407 << std::setw(2) << roc_num
409 <<
" Bank [index,id]["
423 vme_slot_num = slot_id;
426 <<
"Slot [id, VME num] ["
427 << std::setw(2) << slot_id
429 << std::setw(2) << vme_slot_num
431 if ( module_index == -1 ) {
433 <<
"Unused in R1 SciFiDetector"
439 << module_index << std::endl;
445 for(
size_t midx = 0; midx <
fDetectorIDs.size(); midx++ )
447 for (
size_t chan = 0 ; chan<
fDetectorIDs.at(midx).size(); chan++)
449 std::cout <<
"[" << midx <<
","<< chan <<
"] "
471 for ( j=0; j<(num_words/5); j++ )
473 printf (
"buffer[%5d] = 0x:", ipt );
474 for ( k=j; k<j+5; k++ )
476 printf (
"%12x", buffer[ipt++] );
481 if ( ipt<num_words ) {
482 printf (
"buffer[%5d] = 0x:", ipt );
483 for ( k=ipt; k<num_words; k++ )
485 printf (
"%12x", buffer[ipt++] );
499 const UInt_t bank_id,
504 TString subsystem_name =
"";
506 Int_t bank_index = 0;
509 UInt_t vme_slot_num = 0;
511 Bool_t local_debug =
false;
519 <<
" local_f1tdc " << local_f1tdc <<
"\n";
525 std::cout <<
"-----------------------------------------------------" << std::endl;
527 std::cout <<
"\nQwSciFiDetector : "
530 <<
"ProcessConfigurationBuffer"
533 << std::setw(2) << roc_id
534 <<
" Bank [index,id]["
547 vme_slot_num = slot_id;
550 <<
"Slot [id, VME num] ["
551 << std::setw(2) << slot_id
553 << std::setw(2) << vme_slot_num
561 if (tdc_index not_eq -1) {
563 if(local_f1tdc)
delete local_f1tdc; local_f1tdc = NULL;
565 local_f1tdc =
new QwF1TDC(roc_id, vme_slot_num);
574 std::cout <<
"F1TDC index "
586 std::cout <<
"Unused in "
590 <<
" local_f1tdc at "
598 if (slot_id == 0) std::cout <<
" ";
599 else if (slot_id == 1) std::cout <<
"MVME CPU ";
600 else std::cout <<
"Trigger Interface";
604 std::cout << std::endl;
611 std::cout <<
"-----------------------------------------------------" << std::endl;
620 printf(
"\nQwSciFiDetector::ProcessConfigurationBuffer: \n");
621 printf(
"Bank index is not defined with ROC id %d and Bank id %d. Thus, this is not F1TDC data. Skip this bank\n\n", roc_id, bank_id);
644 const UInt_t bank_id,
649 Int_t bank_index = 0;
650 Int_t vme_module_slot_number = 0;
651 Int_t vme_module_chan_number = 0;
652 UInt_t vme_module_data = 0;
653 Int_t module_index = 0;
655 Bool_t data_integrity_flag =
false;
656 Bool_t temp_print_flag =
false;
660 if (bank_index>=0 && num_words>0) {
664 if ( temp_print_flag ) {
665 std::cout <<
"\nQwSciFiDetector::ProcessEvBuffer: "
666 <<
"Begin processing ROC"
671 <<
" Subbbank Index "
687 if (data_integrity_flag) {
690 for (UInt_t i=0; i<num_words ; i++) {
697 module_index =
GetModuleIndex(bank_index, vme_module_slot_number);
699 if ( vme_module_slot_number == 31) {
719 FillRawTDCWord(bank_index, vme_module_slot_number, vme_module_chan_number, vme_module_data);
722 catch (std::exception&
e) {
723 std::cerr <<
"Standard exception from QwSciFiDetector::FillRawTDCWord: "
724 << e.what() << std::endl;
725 std::cerr <<
" Parameters: index==" <<bank_index
726 <<
"; Slot Number==" <<vme_module_slot_number
727 <<
"; Channel Number=="<<vme_module_chan_number
728 <<
"; Data==" <<vme_module_data
731 std::cerr <<
" Module Index=="<<module_index
732 <<
"; fDetectorIDs.at(module_index).size()=="
734 <<
"; fDetectorIDs.at(module_index).at(chan).fPlane=="
735 <<
fDetectorIDs.at(module_index).at(vme_module_chan_number).fPlane
736 <<
"; fDetectorIDs.at(module_index).at(chan).fElement=="
737 <<
fDetectorIDs.at(module_index).at(vme_module_chan_number).fElement
750 if (buffer[0]/32!=1) {
751 if(temp_print_flag) printf(
"This buffer contains more than one event, thus, we reject them\n");
755 UInt_t words_read = 0;
756 for (std::size_t k=0; k<
fSCAs.size(); k++) {
758 if(temp_print_flag) printf(
"k %d words_read %d\n", (Int_t)k, words_read);
776 Bool_t local_debug =
false;
782 if (tdcindex not_eq -1) {
805 package = fDetectorIDs.at(tdcindex).at(chan).fPackage;
808 printf(
"bank_idx %d, slot %d, plane %d, element %d, package %d\n",
809 bank_index, slot_num, (Int_t) plane, (Int_t) element, (Int_t) package);
812 if (plane == -1 or element == -1){
822 direction =
fDetectorIDs.at(tdcindex).at(chan).fDirection;
847 std::cout <<
"At QwSciFiDetector::FillRawTDCWord "
848 <<
" bank index " << bank_index
849 <<
" slot num " << slot_num
850 <<
" chan num " << chan
851 <<
" hitcnt " << hitcnt
852 <<
" plane " << plane
853 <<
" wire " << element
854 <<
" package " <<
package
855 << " diection " << direction
856 << " fTDCHits.size() " << fTDCHits.size()
940 std::cout<<
"QwSciFiDetector::RegisterSubbank()"
941 <<
" ROC " << current_roc_id
942 <<
" Subbank " << bank_id
969 std::cout <<
"QwSciFiDetector::RegisterSlotNumber: Slot number "
970 << slot_id <<
" is larger than the number of slots per ROC, "
980 Int_t module_index = -1;
983 module_index =
fModuleIndex.at(bank_index).at(slot_num);
996 UInt_t bank_index = 0;
997 Double_t raw_time_arb_unit = 0.0;
998 Double_t ref_time_arb_unit = 0.0;
999 Double_t time_arb_unit = 0.0;
1002 Bool_t local_debug =
false;
1005 TString reference_name1 =
"MasterTrigger";
1006 TString reference_name2 =
"CopyMasterTrigger";
1009 for ( std::vector<QwHit>::iterator hit=
fTDCHits.begin(); hit!=
fTDCHits.end(); hit++ )
1012 bank_index = hit -> GetSubbankID();
1013 slot_num = hit -> GetModule();
1014 raw_time_arb_unit = (Double_t) hit -> GetRawTime();
1015 ref_time_arb_unit =
fF1RefContainer -> GetReferenceTimeAU(bank_index, reference_name1);
1019 if(ref_time_arb_unit==0.0) {
1027 hit -> SetTime(time_arb_unit);
1028 hit -> SetRawRefTime((UInt_t) ref_time_arb_unit);
1032 <<
" BankIndex " << std::setw(2) << bank_index
1033 <<
" Slot " << std::setw(2) << slot_num
1034 <<
" RawTime : " << std::setw(6) << raw_time_arb_unit
1035 <<
" RefTime : " << std::setw(6) << ref_time_arb_unit
1036 <<
" time : " << std::setw(6) << time_arb_unit
1172 for(std::vector<QwHit>::iterator iter=
fTDCHits.begin(); iter!=
fTDCHits.end(); ++iter)
Int_t GetSubbankIndex() const
#define QwMessage
Predefined log drain for regular messages.
void AddQwF1TDC(QwF1TDC *in)
std::map< TString, TString > fDetectorMaps
void ReportConfiguration(Bool_t verbose)
Int_t ProcessConfigurationBuffer(const UInt_t roc_id, const UInt_t bank_id, UInt_t *buffer, UInt_t num_words)
F1TDCs configuration and reference siganls container.
void ClearAllBankRegistrations()
void SetF1TDCBuffer(UInt_t *buffer, UInt_t num_words)
const UInt_t & GetTDCMaxChannels() const
F1TDCReferenceContainer * fF1RefContainer
Double_t fF1TDCResolutionNS
static UInt_t GetUInt(const TString &varvalue)
std::vector< QwHit > fTDCHits
void FillRawTDCWord(Int_t bank_index, Int_t slot_num, Int_t chan, UInt_t data)
std::vector< std::pair< Int_t, Int_t > > fReferenceChannels
void SubtractReferenceTimes()
const UInt_t & GetTDCData() const
Bool_t HasDataLoaded() const
one F1TDC configuration and reference signal(s) holder
void ConstructBranchAndVector(TTree *tree, TString &prefix, std::vector< Double_t > &values)
Construct the branch and tree vector.
Double_t GetReferenceTimeAU(Int_t bank_index, TString name)
Int_t LoadInputParameters(TString mapfile)
Mandatory parameter file definition.
Int_t GetModuleIndex(size_t bank_index, size_t slot_num) const
Bool_t CheckDataIntegrity(const UInt_t roc_id, UInt_t *buffer, UInt_t num_words)
Int_t kNumberOfVMEModules
std::vector< Int_t > fSCAs_offset
UInt_t kMaxNumberOfChannelsPerF1TDC
virtual void ConstructHistograms()
Construct the histograms for this subsystem.
QwF1TDContainer * fF1TDContainer
Int_t ProcessEvBuffer(const UInt_t roc_id, const UInt_t bank_id, UInt_t *buffer, UInt_t num_words)
TODO: The non-event-type-aware ProcessEvBuffer routine should be replaced with the event-type-aware v...
const UInt_t & GetTDCSlotNumber() const
std::vector< std::vector< Int_t > > fModuleIndex
Bool_t IsSlotRegistered(Int_t bank_index, Int_t slot_num) const
const UInt_t & GetTDCChannelNumber() const
void SetEventTypeMask(const UInt_t mask)
Set event type mask.
size_t fTreeArrayIndex
Tree indices.
QwSciFiDetector()
Private default constructor (not implemented, will throw linker error on use)
Int_t RegisterROCNumber(const UInt_t roc_id)
void FillTreeVector(std::vector< Double_t > &values) const
Fill the tree vector.
static const Int_t kF1ReferenceChannelNumber
void FillHardwareErrorSummary()
Hardware error summary.
Double_t ReferenceSignalCorrection(Double_t raw_time, Double_t ref_time, Int_t bank_index, Int_t slot)
void FillHistograms()
Fill the histograms for this subsystem.
void FillListOfHits(QwHitContainer &hitlist)
std::vector< std::vector< Double_t > > fReferenceData
void SetReferenceSignal(Int_t bank_index, Int_t slot, Int_t chan, UInt_t data, Bool_t debug=false)
Double_t DoneF1TDCsConfiguration()
Bool_t WireMatches(EQwRegionID region, EQwDetectorPackage package, Int_t plane, Int_t wire)
Bool_t IsValidDataword() const
The pure virtual base class of all subsystems.
Int_t fCurrentModuleIndex
void SetF1BankIndex(const Int_t bank_index)
const MQwF1TDC GetF1TDCDecoder() const
class QwScaler_Channel< 0x00ffffff, 0 > QwSIS3801D24_Channel
void SetF1SystemName(const TString name)
std::vector< std::vector< UInt_t > > fBank_IDs
Vector of Bank IDs per ROC ID associated with this subsystem.
Int_t fCurrentROC_ID
ROC ID that is currently being processed.
Int_t RegisterSubbank(const UInt_t bank_id)
Tell the object that it will decode data from this sub-bank in the ROC currently open for registratio...
Int_t fCurrentBankIndex
Name of this subsystem (the region).
static const UInt_t kMaxNumberOfSlotsPerROC
virtual Int_t RegisterROCNumber(const UInt_t roc_id, const UInt_t bank_id=0)
Tell the object that it will decode data from this ROC and sub-bank.
void PrintConfigurationBuffer(UInt_t *buffer, UInt_t num_words)
Int_t LoadChannelMap(TString mapfile)
Mandatory map file definition.
std::vector< UInt_t > fROC_IDs
Vector of ROC IDs associated with this subsystem.
void SetF1TDCIndex(const Int_t tdc_index)
Hit structure uniquely defining each hit.
void Print(const Option_t *options=0) const
std::map< TString, size_t > fSCAs_map
Int_t RegisterSubbank(const UInt_t bank_id)
Int_t RegisterSlotNumber(const UInt_t slot_id)
void DecodeTDCWord(UInt_t &word, const UInt_t roc_id)
std::vector< QwSIS3801D24_Channel > fSCAs
size_t fTreeArrayNumEntries
std::vector< std::vector< QwDetectorID > > fDetectorIDs
void ClearAllBankRegistrations()
Clear all registration of ROC and Bank IDs for this subsystem.
#define RegisterSubsystemFactory(A)
TString GetSubsystemName() const
virtual ~QwSciFiDetector()
void SetDataLoaded(Bool_t flag)