49 Int_t current_roc_id = -1;
50 Int_t current_bank_id = -1;
52 Int_t current_logical_accum = 0;
53 std::vector<TString> name;
54 std::vector<std::vector<TString> > accums;
55 std::vector<std::vector<Double_t> > weights;
61 while (mapstr.ReadNextLine()) {
63 mapstr.TrimWhitespace();
64 if (mapstr.LineIsEmpty())
continue;
66 TString varname, varvalue;
67 if (mapstr.HasVariablePair(
"=",varname,varvalue)) {
71 if (varname ==
"roc") {
75 }
else if (varname ==
"bank") {
80 }
else if (varname ==
"begin") {
82 name.resize(current_logical_accum+1);
83 accums.resize(current_logical_accum+1);
84 weights.resize(current_logical_accum+1);
86 while(mapstr.ReadNextLine()) {
88 mapstr.TrimWhitespace();
89 if (mapstr.LineIsEmpty())
continue;
92 if (mapstr.HasVariablePair(
"=",varname,varvalue)) {
94 if (varname ==
"end") {
95 current_logical_accum++;
97 }
else if (varname ==
"name") {
98 name[current_logical_accum] = varvalue;
101 accums[current_logical_accum].push_back(mapstr.GetTypedNextToken<TString>());
102 weights[current_logical_accum].push_back(mapstr.GetTypedNextToken<Double_t>());
109 TString modtype = mapstr.GetTypedNextToken<TString>();
110 UInt_t modnum = mapstr.GetTypedNextToken<UInt_t>();
111 UInt_t channum = mapstr.GetTypedNextToken<UInt_t>();
112 TString dettype = mapstr.GetTypedNextToken<TString>();
113 TString name = mapstr.GetTypedNextToken<TString>();
118 if (modtype ==
"SIS3320") {
130 if (iter->first != subbank &&
131 iter->second.size() > modnum &&
132 iter->second.at(modnum).size() > channum &&
133 iter->second.at(modnum).at(channum) >= 0) {
134 QwMessage <<
"Connecting SIS3320 " << name <<
"/" << dettype
136 <<
" in ROC 0x" << current_roc_id <<
", bank 0x" << current_bank_id
140 iter->second.at(modnum).at(channum);
145 QwMessage <<
"Registering SIS3320 " << name <<
"/" << dettype
147 <<
" in ROC 0x" << current_roc_id <<
", bank 0x" << current_bank_id
149 <<
" at mod " << modnum <<
", chan " << channum
155 fSamplingADC.at(index).InitializeChannel(channum, name);
158 }
else if (modtype ==
"V792") {
170 <<
" in ROC 0x" << current_roc_id <<
", bank 0x" << current_bank_id
172 <<
" at mod " << modnum <<
", chan " << channum
181 }
else if (modtype ==
"V775") {
193 <<
" in ROC 0x" << current_roc_id <<
", bank 0x" << current_bank_id
195 <<
" at mod " << modnum <<
", chan " << channum
210 for (
size_t logical = 0; logical < name.size(); logical++) {
211 for (
size_t adc = 0; adc <
fSamplingADC.size(); adc++) {
212 fSamplingADC[adc].AddLogicalAccumulator(name[logical],accums[logical],weights[logical]);
239 while (mapstr.ReadNextLine()) {
240 mapstr.TrimComment();
241 mapstr.TrimWhitespace();
243 TString varname =
"";
244 Double_t varped = 0.0;
245 Double_t varcal = 1.0;
247 if (mapstr.LineIsEmpty())
continue;
249 varname = mapstr.GetTypedNextToken<TString>();
251 varname.Remove(TString::kBoth,
' ');
252 varped = mapstr.GetTypedNextToken<Double_t>();
253 varcal = mapstr.GetTypedNextToken<Double_t>();
257 Bool_t found = kFALSE;
258 for (
size_t i = 0; i <
fSamplingADC.size() && !found; i++) {
261 if (localname == varname) {
262 QwMessage <<
"Setting pedestal and calibration of sampling ADC " << localname
263 <<
" to " << varped <<
" and " << varcal <<
"." <<
QwLog::endl;
302 std::vector<UInt_t> elements;
310 std::vector<UInt_t> subbankheader;
311 std::vector<UInt_t> rocheader;
312 if (elements.size() > 0) {
315 subbankheader.clear();
316 subbankheader.push_back(elements.size() + 1);
317 subbankheader.push_back((
fCurrentBank_ID << 16) | (0x01 << 8) | (1 & 0xff));
322 rocheader.push_back(subbankheader.size() + elements.size() + 1);
323 rocheader.push_back((
fCurrentROC_ID << 16) | (0x10 << 8) | (1 & 0xff));
327 buffer.insert(buffer.end(), rocheader.begin(), rocheader.end());
328 buffer.insert(buffer.end(), subbankheader.begin(), subbankheader.end());
329 buffer.insert(buffer.end(), elements.begin(), elements.end());
344 UInt_t words_read = 0;
349 if (subbank >= 0 && num_words > 0) {
359 for (
size_t channum = 0; channum <
fSamplingADC_Mapping[subbank].at(modnum).size(); channum++) {
362 words_read +=
fSamplingADC[index].ProcessEvBuffer(&(buffer[words_read]), num_words - words_read);
374 UInt_t header = buffer[words_read++];
375 if ((header & 0xbad00dc0) == 0xbad00dc0)
385 for (
size_t i = words_read; i < num_words; i++) {
400 QwDebug <<
"QDC " << std::hex << subbank <<
" "
401 << modnum <<
"," << channum <<
": " << std::dec
414 QwDebug <<
"TDC " << std::hex << subbank <<
" "
415 << modnum <<
"," << channum <<
": " << std::dec
423 words_read = num_words;
437 if (num_words != words_read) {
438 QwError <<
"QwComptonPhotonDetector: There were "
439 << num_words - words_read
440 <<
" leftover words after decoding everything we recognize"
442 <<
" in ROC " << roc_id <<
", bank " << bank_id <<
"."
506 if (!test) std::cerr <<
"This is not a good event!" << std::endl;
623 for (
size_t i = 0; i < innumer->
fSamplingADC.size(); i++)
669 if (value == 0)
return kFALSE;
672 Bool_t result = kTRUE;
673 if (
typeid(*value) !=
typeid(*
this)) {
701 if (value == 0)
return kFALSE;
704 Bool_t result = kTRUE;
705 if (
typeid(*value) !=
typeid(*
this)) {
725 if (value == 0)
return kFALSE;
728 Bool_t result = kTRUE;
729 if (
typeid(*value) !=
typeid(*
this)) {
749 if (value == 0)
return kFALSE;
752 Bool_t result = kTRUE;
753 if (
typeid(*value) !=
typeid(*
this)) {
801 fTree =
new TTree(
"ComptonPhoton",
"Compton Photon Detector");
879 QwOut <<
" sampling ADC " << i <<
":";
883 QwOut <<
" integrating TDC " << i <<
":";
887 QwOut <<
" integrating ADC " << i <<
":";
901 if (adc->GetElementName() == name) {
Int_t GetSubbankIndex() const
#define QwMessage
Predefined log drain for regular messages.
std::vector< QwPMT_Channel > fMultiTDC_Channel
std::map< TString, TString > fDetectorMaps
Class for the decoding of the SIS3320 sampling ADC data.
QwSIS3320_Channel * GetSIS3320Channel(const TString name)
#define QwOut
Predefined log drain for explicit output.
std::vector< QwPMT_Channel > fMultiQDC_Channel
UInt_t GetTDCChannelNumber()
Int_t LoadInputParameters(TString pedestalfile)
Int_t LoadEventCuts(TString &filename)
void Ratio(VQwSubsystem *numer, VQwSubsystem *denom)
void Sum(VQwSubsystem *value1, VQwSubsystem *value2)
Int_t fTree_fNEvents
Expert tree fields.
static UInt_t GetUInt(const TString &varvalue)
std::map< Int_t, ChannelType_t > fMapping
void AccumulateRunningSum(VQwSubsystem *value)
VQwSubsystem & operator=(VQwSubsystem *value)
VQwSubsystem & operator-=(VQwSubsystem *value)
#define QwVerbose
Predefined log drain for verbose messages.
void EncodeEventData(std::vector< UInt_t > &buffer)
virtual void ConstructHistograms()
Construct the histograms for this subsystem.
void CalculateRunningAverage()
Bool_t CompareQDC(VQwSubsystem *source)
void Difference(VQwSubsystem *value1, VQwSubsystem *value2)
IntegratingTDC_Mapping_t fMultiTDC_Mapping
#define QwDebug
Predefined log drain for debugging output.
void ConstructBranchAndVector(TTree *tree, TString &prefix, std::vector< Double_t > &values)
VQwSubsystem & operator+=(VQwSubsystem *value)
static void DefineOptions()
Define options function (note: no virtual static functions in C++)
A logfile class, based on an identical class in the Hermes analyzer.
void ProcessOptions(QwOptions &options)
Process the command line options.
void DecodeTDCWord(UInt_t &word, const UInt_t roc_id=0)
void RandomizeEventData(int helicity=0)
virtual void PrintInfo() const
Print some information about the subsystem.
Bool_t Compare(VQwSubsystem *source)
std::vector< QwSIS3320_Channel > fSamplingADC
Bool_t CompareADC(VQwSubsystem *source)
The pure virtual base class of all subsystems.
Int_t ProcessEvBuffer(const UInt_t roc_id, const UInt_t bank_id, UInt_t *buffer, UInt_t num_words)
Int_t ProcessConfigurationBuffer(const UInt_t roc_id, const UInt_t bank_id, UInt_t *buffer, UInt_t num_words)
SamplingADC_Mapping_t fSamplingADC_Mapping
Int_t fCurrentROC_ID
ROC ID that is currently being processed.
Int_t RegisterSubbank(const UInt_t bank_id)
Tell the object that it will decode data from this sub-bank in the ROC currently open for registratio...
virtual Int_t RegisterROCNumber(const UInt_t roc_id, const UInt_t bank_id=0)
Tell the object that it will decode data from this ROC and sub-bank.
static std::ostream & endl(std::ostream &)
End of the line.
Class for the analysis of Compton photon detector data.
void Scale(Double_t factor)
TTree * fTree
Expert tree.
virtual void ConstructTree()
Construct the tree for this subsystem.
void FillTreeVector(std::vector< Double_t > &values) const
Int_t LoadChannelMap(TString mapfile)
Bool_t CompareTDC(VQwSubsystem *source)
Int_t fCurrentBank_ID
Bank ID that is currently being processed.
IntegratingADC_Mapping_t fMultiQDC_Mapping
#define RegisterSubsystemFactory(A)
#define QwError
Predefined log drain for errors.